1. Field of the Invention
The present invention relates to a high-frequency clock detection circuit installed in a circuit device such as LSI, etc. operating based on a clock frequency and detecting an irregularity that clock frequency is heightened.
This is a counterpart of Japanese patent application Serial Number 283196/2007, filed on Oct. 31, 2007, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
Accounting terminals used in banking systems need to be highly secure. The accounting terminal has a risk of hacking for tampering with the data or stealing the data by attacks from outside or inside enterprises. There are various methods for attacking to LSIs, and one of methods for attacking is heightening intentionally the external clock of LSIs to arise malfunction of CPU in LSIs. Therefore, a clock detecting circuit is necessary to detect a clock frequency other than the predetermined frequency in order to prevent malfunction of the LSIs by the above attack.
FIG. 1 is a general diagram of the conventional clock detection circuit. In the clock detection circuit, reference clock is generated by a ring oscillator for immunity to attack from outside. Counting up is done by the counter A based on the reference clock and the counter B based on the CPU clock, respectively, and it detected whether the frequency of the CPU clock is a high frequency of the high frequency clock or not, by monitoring the ratio of the CPU clock to the reference clock using the overflow signal of the counters or the counting values.
However, in the example of FIG. 1, since the monitoring and the detection are done at a certain constant period till the counter is overflowed during detecting high-frequency clock, it is impossible to detect an attack by a short-time high-frequency clock such as several to several hundred pulses of high-frequency clock.
In the Japanese Patent Application Laid-Open Publication No. H7-151839, the semiconductor test equipment having capability to prevent malfunction by detecting that the clock signal period exceeds the limit is disclosed. Therefore, it is possible to detect a short-time attack by high-frequency clock by installing the above clock detection circuit in order to prevent hacking.
However, according to the technology disclosed in the Japanese Patent Application Laid-Open Publication No. H7-151839, there is a problem that a limit is put on the clock-signal period to be detected. The above-mentioned technology has a configuration that the detection signal is generated by direct logic addition of the delayed signal waveform, which has the predetermined pulse width as a criterion and is delayed by the clock-signal pulse width, and the clock-signal waveform, wherein the pulse width of the clock signal is fixed. In other words, in the case where the clock-signal period varies and the clock-signal pulse width also varies, it is not considered that there is a case where the faster becomes the clock, the shorter becomes the pulse width, while the duty ratio is fixed. For example, it must be determined that all the pulse periods having a pulse width shorter than 15 nsec are irregular, while the 15 nsec pulse width has been predetermined.
The present invention has been invented in the consideration of the above-mentioned problem, and the object of the invention is to provide a high-frequency clock detection circuit having capability to detect high-frequency clock signal using any period as a threshold.
A high-frequency clock detection circuit according to the present invention detects a irregular state of the high frequency in the clock signal after taking in the clock signal from the function circuit operating according to the clock signal, and the high-frequency clock detection circuit includes a delay circuit, a first flip-flop circuit, a second flip-flop circuit, and a detecting-result output circuit. To the delay circuit, a delay time longer than a period corresponding to the irregular state of the high frequency is set. The first flip-flop circuit delay flip-flops according to the clock signal, and the output signal becomes an inverted-feedback input thereto. The second flip-flop circuit delay flip-flops according to the clock signal, and the output signal becomes an inverted-feedback input thereto. The detecting-result output circuit detects the difference between the output signal from the first flip-flop circuit and the output signal from the second flip-flop circuit, and provides the function circuit with a high-frequency-clock detection signal indicating the irregular state of the high frequency corresponding to occurrence of the differential.